View AD7902_8874872.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

dual pseudo differential 16 - bit, 1 msps pulsar adc 12 .0 mw in q sop data sheet AD7902 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 C 2015 analog devices, inc. all rights reserved. technical support www.analog.com features 1 6 - bit resolution with no missing codes throughput: 1 msps low power dissipation 7.0 mw at 1 msps (v dd 1 and v dd2 o nly) 12 .0 mw at 1 msps (t otal) 140 w at 10 ksps inl: 1.0 lsb typica l, 2.5 lsb m aximum sinad: 91 db at 1 khz thd: ? 105 db at 1 khz pseudo differential analog input range 0 v to v ref with v ref between 2. 4 v to 5. 1 v a llows use of a ny input range easy to drive with the ada4841 - 1 / ada4841 - 2 no pipeline delay single - supply 2.5 v operation with 1.8 v/2.5 v/3 v/5 v logic interface serial port interface ( spi ) qspi/microwire/dsp compatible 2 0 - lead qsop package wide operating temperature range: ?40c to +125c applications battery - powered equipment communications automated test equipment ( ate ) data acquisition medical instrumentation redundant measurement simultaneous s ampling general description the AD7902 is a dual 1 6 - bit, successive approximation, analog - to - digital converter (adc) that operates from a single power supply, vdd x, per adc . it conta ins two low power, high speed, 1 6 - bit sampling adc s and a versatile serial port interface (spi) . on the cnv x rising edge, the AD7902 sample s an analog input , in+ , in the range of 0 v to v ref with respect to a ground sense , in?. the externally applied reference voltage of the ref x pins ( v ref ) can be set independent ly from the supply voltage pins , vdd x . the power of the device scales linearly with throughput. u sing the sdi x input s, t he spi - compatible serial interface can also daisy - chain multiple adcs on a single 3 - wire bus and provide an optional busy indicator. it is compatible with 1.8 v, 2.5 v, 3 v, or 5 v logic, using the separate vio x supplies . the AD7902 is available in a 2 0 - lead q sop package with operation specified from ? 4 0c to + 125 c. table 1 . msop 14 - /16 - /18 - bit pulsar ? adc s bits 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps adc driver 18 ad7691 1 ad7690 1 ad7982 1 ada4941 - 1 ada4841 - 1 ada4841 - 2 16 ad7680 ad7685 1 ad7686 1 ad7980 1 ada4941 - 1 ad7683 ad7687 1 ad7688 1 ad7903 ada4841 - 1 ad7684 ad7694 ad7693 1 AD7902 ada4841 - 2 14 ad7940 ad7942 1 ad7946 1 1 pin - for - pin compatible. function al block diagram figure 1. gnd vdd1 vdd2 2.5v ref1 ref2 ref = 2.5v to 5v adc1 in1+ in1? vio1 sdi1 sck1 cnv1 sdo1 vio1/vio2 sdi1/sdi2 sck1/sck2 cnv1/cnv2 sdo1 adc2 in2+ in2? vio2 sdi2 sck2 cnv2 sdo2 sdo2 3-wire or 4-wire interface (spi, cs, and chain modes) AD7902 0v to vref 0v to vref 1 1756-001
AD7902* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? AD7902 evaluation board documentation application notes ? an-742: frequency domain response of switched- capacitor adcs ? an-877: interfacing to high speed adcs via spi ? an-931: understanding pulsar adc support circuitry ? an-935: designing an adc transformer-coupled front end data sheet ? AD7902: dual pseudo differential 16-bit, 1 msps pulsar adc 12.0 mw in qsop data sheet product highlight ? [no title found] product highlight ? lowest-power 16-bit adc optimizes portable designs (eeproductcenter, 10/4/2006) user guides ? ug-608: evaluating the AD7902 dual pseudo differential, 16-bit, 1 msps pulsar adc tools and simulations ? AD7902 ibis model reference materials press ? analog devices releases two dual a/d converters with lowest power/highest linearity combination available ? most power efficient drivers for 12-, 14- and 16-bit a/d converters unveiled product selection guide ? sar adc & driver quick-match guide technical articles ? ms-1779: nine often overlooked adc specifications ? ms-2022: seven steps to successful analog-to-digital signal conversion (noise calculation for proper signal conditioning) ? ms-2124: understanding ac behaviors of high speed adcs ? ms-2210: designing power supplies for high speed adc tutorials ? mt-002: what the nyquist criterion means to your sampled data system design ? mt-031: grounding data converters and solving the mystery of "agnd" and "dgnd" design resources ? AD7902 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all AD7902 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
AD7902 data sheet rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 terminology .................................................................................... 13 theory of operation ...................................................................... 14 circuit information .................................................................... 14 converter operation .................................................................. 14 typical connection diagram ................................................... 15 analog inputs ............................................................................. 15 driver amplifier choice ........................................................... 16 voltage reference input ............................................................ 16 power supply ............................................................................... 17 digital interface .......................................................................... 17 cs mode ...................................................................................... 18 chain mode ................................................................................ 22 applications information .............................................................. 24 simultaneous sampling ............................................................. 24 functional saftey considerations ............................................ 25 layout ............................................................................................... 26 evaluating performance of the AD7902 .................................. 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 8/15rev. a to rev. b changed ada4841-x to ada4841-1/ada4841-2 .. throughout change to absolute input voltage parameter, table 2 ................ 3 changes to voltage reference input section .............................. 16 updated outline dimensions ....................................................... 27 7/14rev. 0 to rev. a changed standby current unit from na to a ........................... 4 changes to power supply section ................................................ 17 2/14revision 0: initial version
data sheet AD7902 rev. b | page 3 of 28 specifications v dd = 2.5 v, v io = 2.3 v to 5.5 v, v ref = 5 v, t a = ? 40c to +125c, unless otherwise noted. 1 table 2 . parameter test conditions /comments min typ max unit resolution 16 bits analog input 2 voltage range in x + ? in x? 0 v ref v absolute input voltage in x + ? 0.1 v ref + 0.1 v in x? ? 0.1 0 +0.1 v analog input cmrr f in = 450 khz 67 db leakage current at 25c acquisition phase 200 na accuracy no missing codes 16 bits differential nonl inearity error 3 v ref = 5 v ? 1.0 0.5 +1.0 lsb v ref = 2.5 v 0.8 lsb integral nonl inearity error 3 v ref = 5 v ? 2.5 1.0 +2.5 lsb v ref = 2.5 v 0.9 lsb transition noise 3 v ref = 5 v 0.75 lsb v ref = 2.5 v 1.2 lsb gain error 4 t min to t max ? 0.08 0.012 +0.08 % fs gain error temperature drift 0.3 ppm/c gain error match 4 t min to t max 0.016 0.08 % fs zero error 4 t min to t max ? 1.25 0.25 +1.25 mv zero temperature drift 0.19 ppm/c zero error match 4 t min to t max 0.2 1.0 mv power supply sensitivity 3 v dd = 2.5 v 5% 0.1 lsb throughput conversion rate v io 2.3 v up to 85c, v io 3.3 v above 85c , up to 125c 0 1 msps transient response full - scale step 290 ns ac accuracy 5 dynamic range v ref = 5 v 92 db v ref = 2.5 v 87 db over s ampled dynamic range f o ut = 10 ksps 111 db signal - to - noise ratio ( snr ) f in = 1 khz, v ref = 5 v 89.5 91.5 db f in = 1 khz, v ref = 2.5 v 84.5 86.5 db spurious - free dynamic range ( sfdr ) f in = 1 khz ? 105 db total harmonic distortion ( thd ) f in = 1 khz ? 105 db signal - to - noise - and - distortion ratio (sinad) f in = 1 khz, v ref = 5 v 89 91 db f in = 1 khz, v ref = 2.5 v 84 86 db channel -to - channel isolation f in = 1 0 khz ? 1 12 db 1 t he voltages for the vddx, viox, and refx pins are indicated by v dd , v io , and v ref , respectively. 2 for information regarding input impedance, see the analog input s section . 3 for the 5 v input range, 1 lsb = 76.3 v. for the 2.5 v input range, 1 lsb = 38.2 v . 4 see the terminology section. these specifications include full temperature range variation , but they do not include the error contribution from the external reference. 5 all specifications in decibels (db) are referred to a full - scale input fsr. although these parameters are referred to full scale, they are tested with an input signal at 0.5 db below full scale, unless otherwise specified.
AD7902 data sheet rev. b | page 4 of 28 v dd = 2.5 v, v io = 2.3 v to 5.5 v, t a = ? 40c to +125c, unless otherwise noted. 1 table 3 . parameter test conditions /comments min typ max unit reference voltage range 2.4 5.1 v load current 1 msps, v ref = 5 v , e ach adc 330 a sampling dynamics ? 3 db input bandwidth 10 mhz aperture delay v dd = 2.5 v 2.0 ns aperture delay match v dd = 2.5 v 2.0 ns digital inputs logic levels v il v io > 3 v ? 0.3 + 0.3 v io v v io 3 v ? 0.3 + 0.1 v vio v v ih v io > 3 v 0.7 v io v io + 0.3 v v io 3 v 0.9 v io v io + 0.3 v i il ? 1 +1 a i ih ? 1 +1 a digital outputs data format s traight binary bits pipeline delay no delay, c onversion results available immediately after conversion is complete 0 samples v ol i sink = 500 a 0.4 v v oh i source = ?500 a v io ? 0.3 v power supplies vdd x 2.375 2.5 2.625 v vio x specified performance 2.3 5.5 v viox range f ull r ange 1.8 5.5 v i vddx each adc 1.4 1.6 ma i viox each adc 0.2 0.45 ma standby current 2 , 3 v dd and v io = 2.5 v, 25c 0.35 a power dissipation 10 ksps throughput 140 w 1 msps throughput 12.0 16 mw vdd x only 1 msps throughput 7.0 mw ref only 3.3 mw vio only 1.7 mw energy per conversion 7.0 nj/sample temperature range 4 specified performance t min to t max ? 40 +125 c 1 in this data sheet, the voltages for the vd dx, viox, and refx pins are indicated by v dd , v io , and v ref , respectively. 2 with all digital inputs forced to vio x or to ground, as re quired. 3 during the acquisition phase. 4 contact analog devices, inc. , for the extended temperature range.
data sheet AD7902 rev. b | page 5 of 28 timing specification s ? 40c to +125c, v dd = 2.37 v to 2.63 v, v io = 2.3 v to 5.5 v, unless otherwise stated. see figure 2 and figure 3 for load conditions. see figure 39, figure 41, figure 43, figure 4 5 , figure 47, figure 49 , and figure 51 for timing diagrams. table 4 . parameter symbol min typ max unit conversion time ( cnv x rising edge to data available ) t conv 500 710 ns acquisition time t acq 290 ns time between conversions t cyc vio x above 2.3 v 1000 ns cnv x pulse width ( cs mode) t cnvh 10 ns sck x period ( cs mode) t sck vio x above 4.5 v 10.5 ns vio x above 3 v 12 ns vio x above 2.7 v 13 ns vio x above 2.3 v 15 ns sckx period ( chain mode ) t sck vio x above 4.5 v 11.5 ns vio x above 3 v 13 ns vio x above 2.7 v 14 ns vio x above 2.3 v 16 ns sck x low time t sckl 4.5 ns sck x high time t sckh 4.5 ns sck x falling edge to data remains valid t hsdo 3 ns sck x falling edge to data valid delay t dsdo vio x above 4.5 v 9.5 ns vio x above 3 v 11 ns vio x above 2.7 v 12 ns vio x above 2.3 v 14 ns cnvx or sdix low to sdox, d15 (msb) valid ( cs mode) t en vio x above 3 v 10 ns vio x above 2.3 v 15 ns cnvx or sdix high or last sckx falling edge to sdox high impedance ( cs mode) t dis 20 ns sdix valid setup time from cnvx rising edge ( cs mode ) t ssdicnv 5 ns sdi x valid hold time from cnv x rising edge ( cs mode) t hsdicnv 2 ns sck x valid setup time from cnv x rising edge ( chain m ode ) t ssckcnv 5 ns sck x valid hold time from cnv x rising edge ( chain m ode ) t hsckcnv 5 ns sdi x valid setup time from sck x falling edge ( chain m ode ) t ssdisck 2 ns sdi x valid hold time from sck x falling edge ( chain m ode ) t hsdisck 3 ns sdi x high to sdo x high ( chain m ode with busy indicator) t dsdosdi 15 ns figure 2 . load circuit for digital interface timing figure 3 . voltage levels for timing 500a i ol 500a i oh 1.4v to sdox c l 20pf 1 1756-002 x% viox 1 y% viox 1 v ih 2 v il 2 v il 2 v ih 2 t delay t delay 1 for viox 3.0v, x = 90 and y = 10; for viox > 3.0v, x = 70 and y = 30. 2 minimum v ih and maximum v il used. see specifications for digital inputs parameter in table 3. 1 1756-003
AD7902 data sheet rev. b | page 6 of 28 absolute maximum rat ings table 5 . parameter rating analog inputs in x +, in x ? to gnd 1 ? 0.3 v to v ref + 0.3 v or 1 0 ma supply voltage ref x , vio x to gnd ? 0.3 v to +6.0 v vdd x to gnd ? 0.3 v to +3.0 v vdd x to vio x +3 v to ?6 v digital inputs to gnd ? 0.3 v to v io + 0.3 v digital outputs to gnd ? 0.3 v to v io + 0.3 v storage temperature range ? 65c to +150c junction temperature 150c lead temperature s vapor phase (60 sec) 25 5c i nfrared (15 sec) 26 0c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. esd caut ion 1 see the analog input s section for an explanation of in x + and in x ? .
data sheet AD7902 rev. b | page 7 of 28 pin configuration an d function descripti ons figure 4 . pin configuration table 6 . pin function descriptions pin no. mnemonic type 1 description 1 , 6 ref 1, ref2 ai reference input voltage. the ref x range is 2. 4 v to 5. 1 v. the s e pin s are referred to the gnd pin , and decouple each pin closely to the gnd pin with a 10 f capacitor. 2 , 7 vdd 1, vdd2 p power supplies . 3 , 8 in 1 + , in 2 + ai pseudo differential positive analog input s . 4 , 9 in 1 ? , in 2 ? ai pseudo differential negative analog input s . 5 , 10 gnd p power supply ground. 11, 16 cnv 2 , c nv 1 di conver sion input s . th ese input s ha ve multiple functions. on the leading edge, they initiate conversions and select the interface mode of the device : chain mode o r active low chip select mode ( cs mode). in cs mode, the sdo x pin s are enable d when the cnv x pins are low. in chain mode , the data must be read when the cnv x pins are high. 12, 17 sdo 2 , sdo 1 do serial data output s . the conversion result is output on th ese pin s . the conversion result is synchronized to sck x . 13, 18 sck 2 , sck 1 di serial data clock input s . when the device is selected, the conversion result s are shifted out by th ese clock s . 14, 19 sdi 2 , sdi 1 di serial data input s . these input s provid e multiple f unction s. they select the interface mode of the adc , as follows: cs mode is selected if the sdi x pins are high during the cnv x rising edge. in this mode, either sdi x or cnv x can enable the serial output signals when low . i f sdi x or cnv x is low when the conversion is complete, the busy indicator feature is enabled. 1 5, 20 vio 2 , vio 1 p input/output interface digital power. nominally at the same supply as the host interface (2.5 v or 3 .3 v). 1 ai is analog input, di is digital input, do is digital output, and p is power . 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 vdd1 in1+ in1? vdd2 ref2 gnd ref1 sdi1 sck1 sdo1 sdi2 vio2 cnv1 gnd in2? in2+ cnv2 sdo2 sck2 vio1 AD7902 top view (not to scale) 1 1756-004
AD7902 data sheet rev. b | page 8 of 28 typical performance characteristics v dd = 2.5 v, v ref = 5.0 v, v io = 3.3 v, t a = 25c , f sample = 1 msps, f in = 10 khz, unless otherwise noted. figure 5 . integral nonlinearity vs. code, v ref = 5 v figure 6 . integral nonlinearity vs. code, v ref = 2.5 v figure 7 . fft plot, v ref = 5 v figure 8 . differential nonlinearity vs. code, v ref = 5 v figure 9 . differential nonlinearity vs. code, v ref = 2.5 v figure 10 . fft plot, v ref = 2.5 v 0 65536 16384 32768 49152 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 inl (lsb) code positive inl: +0.35 lsb negative inl: ?0.90 lsb 1 1756-405 0 65536 16384 32768 49152 positive inl: +0.60 lsb negative inl: ?0.60 lsb 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 inl (lsb) code 1 1756-406 0 500 100 200 300 400 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 snr (db) frequency (khz) f sample = 1msps f in = 10khz snr = 91.37db thd = ?103.7db sfdr = 104.5db sinad = 91.15db 1 1756-407 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 dnl (lsb) code 0 65536 16384 32768 49152 positive dnl: +0.38 lsb negative dnl: ?0.42 lsb 1 1756-408 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 dnl (lsb) code 0 65536 16384 32768 49152 positive dnl: +0.60 lsb negative dnl: ?0.58 lsb 1 1756-409 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 snr (db) frequency (khz) f sample = 1msps f in = 10khz snr = 85.85db thd = ?103.0db sfdr = 105.2db sinad = 85.76db 0 500 100 200 300 400 1 1756-410
data sheet AD7902 rev. b | page 9 of 28 figure 11 . histogram of a dc input at the code center, v ref = 5 v figure 12 . histogram of a dc input at the code transition, v ref = 5 v figure 13 . snr, sinad, and enob vs. reference voltage figure 14 . histogram of a dc input at the code center, v ref = 2.5 v figure 15 . snr vs. input level figure 16 . thd and sfdr vs. reference voltage 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 number of occurrences codes in hex fa6c fa6d fa6e fa6f fa70 fa71 fa72 fa73 fa74 fa75 fa76 210 12406 41352 11317 249 1 1756-4 1 1 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 number of occurrences codes in hex f87c f87d f87e f87f f880 f881 f882 f883 f884 f885 19 3393 31890 28056 2177 1 1756-412 100 98 96 94 92 90 88 86 84 82 80 16.0 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 snr, sinad (db) enob (bits) reference voltage (v) snr sinad enob 1 1756-413 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 number of occurrences codes in hex 135 38 4 3524 2991 521 33 46115 12174 1 1756-414 faba fabb fabc fabd fabe fabf fac0 fac1 fac2 fac3 fac4 fac5 fac6 94 93 92 91 90 89 88 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 ?0.1 snr (db) input level (db) 1 1756-415 ?95 ?125 ?110 ?115 ?105 ?100 ?120 2.25 5.25 reference voltage (v) thd (db) sfdr (db) 2.75 3.25 3.75 4.25 4.75 thd sfdr 100 102 104 106 108 110 112 114 1 1756-416
AD7902 data sheet rev. b | page 10 of 28 figure 17 . sinad vs. input frequency figure 18 . snr vs. temperature figure 19 . operating currents for each adc vs. supply voltage figure 20 . thd vs. input frequency figure 21 . thd vs. temperature fiure eratin currents for ach c s throuhut 91 80 81 82 83 84 85 86 87 88 89 90 1k 10k input frequency (hz) sinad (db) 100k 1m 1 1756-417 92.5 89.5 90.0 90.5 91.0 91.5 92.0 temperature (c) snr (db) ?55 ?35 ?15 5 25 45 65 85 105 125 1 1756-418 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 current (ma) 2.425 2.475 supply voltage (v) 2.375 2.525 2.575 2.625 i vdd i ref i vio 11756-050 ?90 ?92 ?94 ?96 ?98 ?100 ?102 ?104 ?106 ?108 ?110 1k 10k input frequency (hz) thd (db) 100k 1m 1 1756-420 ?100 ?105 ?110 ?115 temperature (c) thd (db) ?55 ?35 ?15 5 25 45 65 85 105 125 1 1756-421 1.6 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 10 100 sample rate (ksps) current (ma) 1000 i vdd i vio t a = 25c 1 1756-422
data sheet AD7902 rev. b | page 11 of 28 figure 23 . operating currents for each adc vs. temperature figure 24 . zero error vs. temperature figure 25 . gain error vs. temperature fiure owe r - own current for ach c s teerature fiure ero rror match s teerature fiure ain rror match s teerature 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 current (ma) ?55 ?35 ?15 5 25 temperature (c) 45 65 85 105 125 i vdd i ref i vio 11756-053 0.4 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 temperature (c) zero error (mv) ?55 ?35 ?15 5 25 45 65 85 105 125 1 1756-424 0.05 ?0.05 ?0.03 ?0.01 0.01 0.03 temperature (c) gain error (% fs) ?55 ?35 ?15 5 25 45 65 85 105 125 1 1756-425 8 7 6 5 4 3 2 1 0 current (a) ?55 ?35 ?15 5 25 temper a ture (c) 45 65 85 105 125 i vdd + i vio 11756-054 0.4 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 temperature (c) zero error match (mv) ?55 ?35 ?15 5 25 45 65 85 105 125 1 1756-427 0.010 ?0.010 ?0.005 0 0.005 temperature (c) gain error match (% fs) ?55 ?35 ?15 5 25 45 65 85 105 125 1 1756-428
AD7902 data sheet rev. b | page 12 of 28 figure 29 . channel - to - channel isolation vs. temperature figure 30 . channel - to - channel isolation vs. input frequency ?100 ?102 ?104 ?106 ?108 ?110 ?112 ?114 ?116 ?118 ?120 temperature (c) channel-to-channel isolation (db) ?55 ?35 ?15 5 25 45 65 85 105 125 f in = 20khz 1 1756-429 ?100 ?102 ?104 ?106 ?108 ?110 ?112 ?114 ?116 ?118 ?120 1k input frequency (hz) channel-to-channel isolation (db) 100k 1m 10k 1 1756-430
data sheet AD7902 rev. b | page 13 of 28 terminology integral nonlinearity error (inl) i nl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is defined as a level 1? lsb b eyond the last code transition. the deviation is measured from the middle of each code to the tru e straight line ( see figure 32). differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. zero error the first transition should occur at a level ? lsb above analog ground (38.1 v for the 0 v to 5 v range). the zero error is the deviation of the actual transition from that point. zero error match it is th e difference in offsets, expressed in millivolts between the channels of a multichannel converter. it is computed with the following equation: zero matching = v zero max ? v zero min where: v zero max is the most positive zero error. v zero min is the most negati ve zero error. zero error matching is usually expressed in millivolts with the full - scale input range stated in the product data sheet. gain error the last transition (from 111 10 to 111 11 ) should occur for an analog voltage 1 ? lsb below the nominal full scale ( 4.999886 v for the 0 v to 5 v range). the gain error is the deviation of the actual level of the last transition from the ideal level after the offset is adjusted out. gain error match it i s the ratio of the maximum full scale to the minimum full scale of a multichannel adc. it is expressed as a percentage of full scale using the following equation: % 100 2 ? ? ? ? ? ? ? = n min max fsr fsr matching gain where: fsr max is the most positive gain error of the adc. fsr min is t he most negative gain error. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution w ith a sine wave input. it is related to sinad by the following formula : enob = ( sinad db ? 1.76)/6.02 enob is expressed in bits. noise free code resolution noise free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. it is calculated as follows: noise free code resolution = log 2 (2 n / peak - to - peak noise ) noise free code resolution is expressed in bits. effective resolution effective resolution is calculated as follows: effective resolution = log 2 (2 n / rms input noise ) effective resolution is expressed in bits . total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expressed in decibels ( db ) . dynamic range dy namic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels ( db ) . it is measured with a signal at ?60 dbf s to include all noise sources and dnl artifacts. signal -to - noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels ( db ) . s ignal -to -n oise - and -d istortion r atio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding d c. the value for sinad is expressed in decibels ( db ) . aperture delay aperture delay is the measure of the acquisition performance. it is the time between the rising edge of the cnv x input and when the input signal is held for a conversion. transient respon se transient response is the time required for the adc to accurately acquire its input after a full - scale step function is applied.
AD7902 data sheet rev. b | page 14 of 28 theory of operation figure 31 . adc simplified schematic circuit information the AD7902 is a fast, low p ower, precise, dual 16 - bit adc using a successive approximation architecture. the AD7902 is capable of simultaneously converting 1,000,000 samples per second (1 msps) and powers down between con - versions. when operating at 10 ksps, for example, it typically consumes 70 w per adc , making it ideal for battery - powered applications. the AD7902 provides the user with an on - chip track - and - hold and does not exhibit any pipeline delay or latency, making it ideal for multi channe l multiplexed applications. the AD7902 can be interfaced to any 1.8 v to 5 v digital logi c family. it is available in a 2 0 - lead qsop that allows for flexible configurations. the device is pin - fo r - pin compatible with the d ifferential , 16 - bit ad7903 . converter operation the AD7902 is a dual successive approximation adc based on a ch arge redistribution dac. figure 31 shows the simplified schematic of the adc. the capacitive dac consis ts of two identical arrays of 16 binary - weighted capacitors, w hich are connected to the two comparator inputs. during the acquisition phase of each adc , terminals of the array tied to the input of the comparator are connected to gnd via the switches, sw x + and sw x ? . all independent switches are connected to the analog inputs. therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in x + and in x ? inputs. when the acquisition phase is complete and the cnv x input goes high, a conversion phase is initiated. when the conversion phase begins, sw x + and sw x ? are opened first. the two capacitor arrays are then disconnected from the inputs and connected to the gnd input. therefore, the differential voltage between the in x + and in x ? inputs , captured at the end of the acquisition phase , is applied to the comparator inputs, causing the comparator to become unbalanced. by switching each element of the capacitor array between gnd and ref x , the comparator input varies by binary - weighted voltage steps (v ref /2, v ref /4 ... v ref /65 ,536 ). the co ntrol logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the device returns to the acquisition phase, and the control logic generates the adc output code and a busy signal indicator. because the AD7902 has an on - board conversion clock, the serial clock, sck x , is not required for the conversion process. transfer functions the ideal transfe r characteristic for the AD7902 is shown in figure 32 and table 7 . figure 32 . adc ideal transfer function tale 7 . output codes and ideal input voltages description analog input, v ref = 5 v digital output code (hex) fsr ? 1 lsb 4.999924 v ffff 1 midscale + 1 lsb 2.500076 v 8001 midscale 2.5 v 8000 midscale ? 1 lsb 2.499924 v 7fff ? fsr + 1 lsb 76.3 v 0001 ? fsr 0 v 0000 2 1 this is also the code for an overranged analog input (v in+ ? v in? above v ref ? v gnd ). 2 this is also the code for an underranged analog input (v in+ ? v in? below v gnd ). comp switches control busy output code cnvx control logic swx+ lsb swx? lsb inx+ refx gnd inx? msb msb c c 4c 2c 16,384c 32,768c c c 4c 2c 16,384c 32,768c 11756-011 000 ... 000 000 ... 001 000 ... 010 111 ... 101 111 ... 110 111 ... 111 ?fsr ?fsr + 1 lsb ?fsr + 0.5 lsb +fsr ? 1 lsb +fsr ? 1.5 lsb analog input adc code (straight binary) 11756-012
data sheet AD7902 rev. b | page 15 of 28 typical connection d iagram figure 35 shows an example of the recommended connection diagram for the AD7902 when multiple supplies are available. analog input s figure 33 shows an equivalent circuit of the input structure of the AD7902 . the two diodes, d1 and d2, provide esd protection for the analog inputs, inx+ and inx?. t he analog input signal must not exceed the reference input voltage ( v ref ) by more than 0.3 v. if the analog input signal exceeds this level, the diodes become forward - biased and start conducting current. these diodes can handle a forward - biased current of 130 ma maximum. however, if the supplies of the input buffer (for example, the supplies of the ada4841 - 1 i n figure 35 ) are different from those of the v ref , the analog input signal may eventually exceed the supply rails by more than 0.3 v. in such a case (for exampl e, an input buffer with a short circuit), the current limitation can be used to protect the device . figure 33 . equivalent analog input circuit the analog input structure allows for the sampling of the differential signal between in x + and in x ? . by using these differential inputs, signals common to both inputs , and within the allowable common - mode input range , are rejected. figure 34 . analog input cmrr vs. frequency during the acquisition p hase, the impedance of the analog inputs (inx+ or inx?) can be modeled as a parallel combination of the c pin c apacitor and the network formed by the series con nection of r in and c in . c pin is primarily the pin capacitance. r in is typically 400 ? and is a lu mped component composed of serial resistors and the on resistance of the switches. c in is typically 30 pf and is mai nly the adc sampling capacitor. during the sampling phase, where the switches are closed, the input impedance is limited to c pin . r in and c in make a one - pole, low - pass filter that reduces undesirable aliasing effects and limits noise. when the source impedance of the driving circuit is low, the AD7902 can be driven directly. large so urce impedances significantly affect the ac performance, especially thd. the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the s ource impedance and the maximum input frequency. figure 35 . typical application diagram with multiple supplies c pin refx r in c in d1 d2 inx+ or inx? gnd 11756-114 90 85 80 75 70 65 60 1k 10k 100k 1m 10m frequency (hz) cmrr (db) 11756-040 AD7902 adcx 3-wire interface 2.5v v+ 1.8v to 5v 100nf c ref 10f 2 100nf refx inx+ inx? vddx viox sdix cnvx sckx sdox gnd ref 1 20 v+ v? 0v to v ref 2.7nf 4 1 see the voltage reference input section for reference selection. 2 c ref is usually a 10f ceramic capacitor (x5r). see recommended layout in figure 53. 3 see the driver amplifier choice section. 4 optional filter. see the analog inputs section. 11756-013 ada4841-1 3
AD7902 data sheet rev. b | page 16 of 28 driver amplifier choice although the AD7902 is easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier must be kept as low as possible to preserve the snr and transition noise performance of the AD7902 . the noise from the driver is filtered by the one-pole, low-pass filter of the AD7902 analog input circuit, made by r in and c in or by the external filter, if one is used. because the typical noise of the AD7902 is 56 v rms, the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 2 )( 2 47.3 47.3 log20 n 3db loss nef snr where: f ?3db is the input bandwidth, in megahertz, of the AD7902 (10 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for example, gain = 1 in buffer configuration; see figure 35). e n is the equivalent input noise voltage of the op amp, in nv/hz. ? for ac applications, the driver must have a thd performance that is commensurate with the AD7902. ? for multichannel, multiplexed applications, the driver amplifier and the AD7902 analog input circuit must settle for a full-scale step onto the capacitor array at a 16-bit level (0.0015%, 15 ppm). in the amplifier data sheet, settling at 0.1% to 0.01% is more commonly specified. this may differ significantly from the settling time at a 16-bit level. be sure to verify the settling time prior to driver selection. table 8. recommended driver amplifiers amplifier typical application ada4841-1 / ada4841-2 very low noise, small, and low power ad8021 very low noise and high frequency ad8022 low noise and high frequency op184 low power, low noise, and low frequency ad8655 5 v single supply, low noise ad8605 , ad8615 5 v single supply, low power voltage reference input the AD7902 voltage reference input, ref, has a dynamic input impedance and must therefore be driven by a low impedance source with efficient decoupling between the refx and gnd pins, as explained in the layout section. when ref is driven by a very low impedance source (for example, a reference buffer using the ad8031 or the ad8605), a 10 f (x5r, 0805 size) ceramic chip capacitor is appropriate for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference used. for instance, a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift adr430, adr431 , adr433 , adr434 , or adr435 reference. if desired, a reference decoupling capacitor with values as small as 2.2 f can be used with a minimal impact on performance, especially dnl. regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the refx and gnd pins.
data sheet AD7902 rev. b | page 17 of 28 power supply the AD7902 uses two power supply pins per adc : a core supply (vdd x ) and a digital input/output interface supply (vio x ). vio x allows direct interface with any logic between 1.8 v and 5.5 v. to reduce the number of supplies needed, vio x and vdd x can be tied together. the AD7902 is independent of power supply sequencing between vio x and vdd x . additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 36. figure 36 . psrr vs. frequency the AD7902 powers down automatically at the end of each conversion phase; therefore, the power scales linearly with the sampling rate. this makes the device ideal for low sampling rates (of even a few hertz) and low battery - powered applications. figure 37 . operating currents per adc vs. sampling rate digital interface although the AD7902 has a reduced number of pins, it offers flexibility in its serial interface modes. when in cs mode, the AD7902 is compatible with spi, qspi, digital hosts, and dsps. in this mode, the AD7902 can use either a 3 - wire or 4 - wire interface. a 3 - wire interface using the cnv x , sck x , and sdo x signals minimizes wiring connections useful, for instance, in isolated applications. a 4 - wire in terface using the sdi x , cnv x , sck x , and sdo x signals allows cnv x , which initiates the conversions, to be independent of the readback timing (sdi x ). this is useful in low jitter sampling or simultaneous sampling applications. when i n chain mode , the AD7902 provides a daisy - chain feature using the sdi x input for cascading multiple adcs on a single data line similar to a shift register. with the AD7902 housing two adcs in one package, chain mode can be utilized to acquire data from both adcs while using only one set of 4 - wire user interface signals. the mode in which the device opera tes depends on the sdi x level when the cnv x rising edge occurs. cs mode is selected if sdi x is high, and chain mode is selected if sdi x is low. the sdi x hold time is such that when sdi x and cnv x are connected to gether, chain mode is always selected. in either mode, the AD7902 offers the option of forcing a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data read ing . otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. the busy indicator feature is enabled as follows: ? in cs mode when cnv x or sdi x is low when the a dc conversion ends (see figure 41 and figure 45). ? in chain mode when sck x is high during the cnv x rising edge (see figure 49). 95 90 85 80 75 70 65 60 psrr (db) 1k 10k 100k 1m frequency (hz) 11756-139 10 1 0.1 0.01 0.001 operating currents (ma) 100000 sampling rate (sps) 10000 1000000 i ref i vdd i vio 1 1756-137
AD7902 data sheet rev. b | page 18 of 28 cs mode cs mode, 3 - wire interface without busy indicator cs m ode, using a 3 - wire interface without a busy i ndicator , is usually used when a single AD7902 is connected to a spi - compatible digital host. the connection diagram is shown in figure 38 , and the corresponding timing diagram is shown in figure 39. w ith sdi x tied to vio x , a rising edge on cnv x initiates a conversion, selects cs mode, and forces sdo x to high impedance. when a conversion is initiated, it continues until completion , regardless of the state of cnv x . this can be usef ul, for instance, to bring cnv x low to select other spi devic es, such as analog multiplexers . h owever, to avoid generation of the busy signal indicator , cnv x must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time. when the conversion is complete, the AD7902 enters the acquisition phase and powers down. when cnv x goes low, the msb is automatically output onto sdo x . the remai ning data bits are clocked by subsequent sck x falling edges. the data is valid on both sck x edges. although the rising edge can be used to capture the data, a digital host using the falling edge of sck x allows a faster reading rate, provided that it has an ac ceptable hold time. after the 16 th sck x falling edge or when cnv x goes high (whichever occurs first), sdo x returns to high impedance. figure 38 . cs mode, 3 - wire interface without a busy indicator connection diagram (sdi x high) figure 39 . cs mode, 3 - wire interface without a busy indicator serial interface timing (sdi high) AD7902 sdix sdox cnvx sckx convert data in clk digital host viox 11756-116 sdix = 1 t cnvh t conv t cyc cnvx acquisition acquisition t acq t sck t sckl conversion sckx t en t hsdo 1 2 3 14 15 16 t dsdo t dis t sckh sdox d15 d14 d13 d1 d0 11756-216
data sheet AD7902 rev. b | page 19 of 28 cs mode, 3 - wire interface with busy indicator cs mode , using a 3 - wire interface with a busy indicator, is usually used when a single AD7902 is connected to an spi - compatible digital host having an interrupt input. the connection diagram is shown in figure 40 , and the corresponding timing is shown in figure 41. with sdi x tied to vio x , a rising edge on cnv x initiates a conversion, selects cs mode, and forces sdo x to high impedance. sdo x is m aintained in high impedance until the completion of the conversion , regardless of the state of cnv x . prior to the minimum conversion time, cnv x can be used to select other spi devices, such as analog multiplexers, but cnv x must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo x goes from high impedance to low im pedance. with a pull - up on the sdo x line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. the AD7902 then enters the acquisition pha se and powers down. the data bits are then clocked out, msb first, by subsequent sck x falling edges. the data is valid on both sck x edges. although the rising edge can be used to capture the data, a digital host using the sck x falling edge allows a faster reading rate, provided that it has an acceptable hold time. after the optional 17 th sck x falling edge or when cnv x goes high (whichever occurs first), sdo x returns to high impedance. if multiple adc s are selected at the same time, the sdo x output pin handl es this contention without damage or induced latch - up. meanwhile, it is recommended that this contention be kept as short as possible to limit extra power dissipation. figure 40 . cs mode, 3 - wire interface with a busy indicator connection diagram (sdi x high) figure 41 . cs mode, 3 - wire interface with a busy indicator serial interface timing (sdi x high) AD7902 sdix sdox cnvx sckx convert data in clk digital host viox irq viox 47k? 11756-118 t conv t cnvh t cyc acquisition acquisition t acq t sck t sckh t sckl conversion sckx cnvx sdix = 1 sdox d15 d14 d1 d0 t hsdo 1 2 3 15 16 17 t dsdo t dis 11756-218
AD7902 data sheet rev. b | page 20 of 28 cs mode, 4 - wire interface without busy indicator cs mode , using a 4 - wire interface without a busy indicator, is usually used when both adcs within the AD7902 are connected to a spi - compatible digital host. see figure 42 for a n AD7902 conn ection diagram example . t he corresponding timing diagram is shown in figure 43. with sdi x high, a rising edge on cnv x initiates a conversion, selects cs mode, and forces sdo x to high impedance. in this mode, cnv x must be held high during the conver sion phase and the subsequent data readback. (if sdi x and cnv x are low, sdo x is driven low.) prior to the minimum conversion time, sdi x can be used to select other spi devices, such as analog multiplexers, but sdi x must be returned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the AD7902 enters the acq uisition phase and powers down. each adc result can be read by bringing its respective sdi x input low, which consequently outputs the msb onto sdo x . the r emaining data bits are then clocked by subsequent sck x falling edges. the data is valid on both sck x edges. although the rising edge can be used to capture the data, a digital host using the sck x falling edge allows a faster reading rate, provided it has an acceptable hold time. after the 1 6 th sck x falling edge or when sdi x goes high (whichever occurs fi rst), sdo x returns to high impedance , and another adc result can be read. figure 42 . cs mode, 4 - wire interface without a busy indicator connection diagram figure 43 . cs mode, 4 - wire interface without a busy indicator serial interface timing AD7902 adc2 sdi2 sdo2 cnv2 sck2 convert data in clk digital host cs1 cs2 AD7902 adc1 sdi1 sdo1 cnv1 sck1 11756-120 t conv t cyc acquisition acquisition t acq t sck t sckh t sckl conversion sckx cnvx t ssdicnv t hsdicnv sdox d 1 15 d 1 13 d 1 14 d 1 1 d 1 0 d 2 15 d 2 14 d 2 1 d 2 0 t hsdo t en 1 2 3 14 15 16 17 18 30 31 32 t dsdo t dis sdi1 (cs1) sdi2 (cs2) 11756-220
data sheet AD7902 rev. b | page 21 of 28 cs mode, 4 - wire interface with busy indicator cs mode , 4 - wire with busy indicator, is usually used when a n AD7902 is con nected to a spi - compatible digital host with an interrupt input . this cs mode is also used when it is desir able to keep cnv x , which is used to sample the analog input, indepen - dent of the signal that is used to select the data reading. this independence is particularly important in applications where low jitter on cnv x is desired. the connection diagram is shown in figure 44 , and the corresponding timing is given in figure 45. with sdi x high, a rising edge on cnv x initiates a conversion, selects cs mode, and forces sdo x to high impedance. in this mode, cnv x must be held high during the conversion phase and the subsequent data readback. (if sdi x and cnv x a re low, sdo x is driven low.) prior to the minimum conversion time, sdi x can be used to select other spi devices, such as analog multiplexers, but sdi x must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo x goes from high impedance to low impe dance. with a pull - up on the sdo x line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the AD7902 then enters the acquisition phas e and powers down. the data bits are then clocked out, msb first, by subsequent sck x falling edges. the data is valid on both sck x edges. although the rising edge can be used to capture the data, a digital host using the sck x falling edge allows a faster r eading rate, provided that it has an acceptable hold time. after the optional 17 th sck x falling edge or sdi x going high (whichever occurs first), sdo x returns to high impedance. figure 44 . cs mode, 4 - wire interface with a busy indicator connection diagram figure 45 . cs mode, 4 - wire interface with a busy indicator serial interface timing AD7902 sdix sdox cnvx sckx convert data in clk digital host irq viox 47k? cs1 11756-122 t conv t cyc acquisition t ssdicnv acquisition t acq t sck t sckh t sckl conversion sdix t hsdicnv sckx cnvx sdox t en d15 d14 d1 d0 t hsdo 1 2 3 15 16 17 t dsdo t dis 11756-222
AD7902 data sheet rev. b | page 22 of 28 chain mode chain mode without busy indicator c hain mode without a busy indicator can be use d to daisy - chain both adcs within an AD7902 on a 3 - wire serial interface. this feature is useful for red ucing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. see figure 46 for a conn ection diagram example using both adcs in an AD7902 . t he corresponding timing is shown in figure 47. when sdi x and cnv x are low, sdo x is driven low. with sck x low, a rising edge on cnv x initiates a conversion, selects chain mode, and disables the busy indicator. in this mode, cnv x is h eld high during the conversion phase and the subsequent data readback. when the conversion is complete, the msb is output onto sdo x and the AD7902 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are clocked by subsequent sck x falling edges. for each adc, sdi x feeds the input of the internal shift register and is clocked by the sck x falling edge. each adc in the chain outputs its data msb f irst, and 1 6 n clocks are required to read back the n adcs. the data is valid on both sck x edges. although the rising edge can be used to capture the data, a digital host using the sck x falling edge allows a faster reading rate and , consequently , more AD7902 devices in the chain, provided that the digital host has an acceptable hold time. the maximum conversion rate may be reduced due to the total readback time. figure 46 . chain mode without a busy indicator connection diagram figure 47 . chain mode without a busy indicator serial interface timing convert data in clk digital host AD7902 adc2 sdi2 sdo2 cnv2 sck2 AD7902 adc1 sdi1 sdo1 cnv1 sck1 11756-124 t conv t cyc t ssdisck t sckl t sck t hsdisck t acq acquisition t ssdicnv acquisition t sckh conversion sdo1 = sdi2 t hsdicnv sckx cnvx sdi1 = 0 sdo2 t en d 1 15 d 1 14 d 1 13 d 2 15 d 2 14 d 2 13 d 2 1 d 2 0 d 1 15 d 1 14 d 1 0 d 1 1 d 1 1 d 1 0 t hsdo 1 2 3 15 16 17 14 18 30 31 32 t dsdo 11756-224
data sheet AD7902 rev. b | page 23 of 28 chain mode with busy indicator c hain mode with a busy indicator can also be used to daisy - chain both adcs within an AD7902 on a 3 - wire serial interface while providing a busy indicator. this feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with limited interfacing capacity. data readback is analogous to clocking a shift re gister. see figure 48 for a connect ion diagram example using three AD7902 adcs . t he corresponding timing is shown in figure 49. when sdi x and cnv x are low, sdo x is driven low. with sck x high, a rising edge on cnv x initiates a conversion, selects chain mode, and enables the busy indicator feature. in this mode, cnv x is held high during the conversion phase and the subsequent data readback. when all adcs in the chain have completed their conversions, the sdo x pin of the adc closest to the digital host (see the adc labeled adcx in the AD7902 b box in figure 48 ) is driven high. this transition on sdo x can be used as a busy indicator to trigger the data readback controlled by the digital host. the AD7902 then enters the acquisition phase and powers down. the data bits stored in the internal shift register are clocked out, msb first, by subsequent sck x falling edges. for each adc, sdi x feeds the input of the internal shift register and is clock ed by the sck x falling edge. each adc in the chain outputs its data msb first, and 16 n + 1 clocks are required to read back the n adcs. although the rising edge can be used to capture the data, a digital host using the sck x falling edge allows a faster reading rate and , consequently , more ad cs in the chain, provided that the digital ho st has an acceptable hold time. figure 48 . chain mode with a busy indicator connection diagram figure 49 . chain mode with a busy indicator serial interface timing convert data in clk digital host AD7902 sdixb sdoxb cnvx sckx AD7902 AD7902 a AD7902 b sdi1a sdo1a cnvx sckx irq AD7902 sdi2a sdo2a cnvx adcx adc1 adc2 sckx notes 1. dashed line denoted adcs are within a given package. 2. sdi1a and sdo1a refer to the sdi1 and sdo1 pins in adc1 in the first AD7902 of the chain (AD7902 a). sdi2a and sdo2a refer to the sdi2 and sdo2 pins in adc2 of AD7902 a. likewise, sdixb and sdoxb refer to the sdix and sdox pins in both adc1 and adc2 of the second AD7902 in the chain (AD7902 b). 11756-126 t conv t cyc t ssdisck t sckh t sck t hsdisck t acq t dsdosdi t dsdosdi t dsdodsi acquisition t ssckcnv acquisition t sckl conversion t hsckcnv sckx cnvx = sdi1 a sdo1 a = sdi2 a sdo2 a = sdix b sdox b t en d a1 15 d a1 14 d a1 13 d a2 15 d a2 14 d a2 13 d bx 15 d bx 14 d bx 13 d a2 1 d a2 0 d a1 15 d a1 14 d a1 1 d a1 0 d bx 1 d bx 0 d a2 15 d a2 14 d a1 0 d a1 1 d a2 0 d a2 1 d a1 14 d a1 15 d a1 1 d a1 0 t hsdo 1 2 3 15 16 17 4 18 19 31 32 33 34 35 47 48 49 t dsdo t dsdosdi t dsdosdi 11756-226
AD7902 data sheet rev. b | page 24 of 28 application s information simultaneous s ampling by having two unique user interfaces, the AD7902 provides maximum flexibility with respect to how conversion results are accessed from the device. the AD7902 provides an option for the two user interfaces to share the convert start (cnv x ) signal from the digital host , creating a 2 - channel , simultaneous sampling device. in applications such as control applications, where latency between the sampling instant and the availability of re sults in the digital host is critical, it is recommended that the AD7902 be configure d as shown in figure 50 . this configuration allows simultaneous data read , in addi tion to simultaneous sampling. however, this configuration also require s an additional data input pin on the digital host. this scena rio allow s for the fastest throughput because it requires only 15 or 16 sck x falling edges (depending on the status of the busy indicator ) to acquire data from the adc. alternatively, for applications where simultaneous sampling is require d but pins on the digital host are limi ted, the two user interfaces on the AD7902 can be connected in one of the daisy - chain configuration s s hown in figure 46 and figure 48 . this daisy chaining allow s the user to implement simultaneous sampling functionality while requiring only one digital host input pin. this scenario require s 31 or 32 sck x falling edges (depen ding on the status of the busy indicator) to acquire data from the adc . figure 50 shows a n example of a simultaneous sampling system using two data inputs for the digital host. the corresponding timing diagram in figure 51 shows a cs mode , 3 - w ire simul - taneous sampling serial interface with out busy i ndicator. however, any of the 3 - wire or 4 - wire serial interface timing options can be used. figure 50 . potential simultaneous sampling connection diagram figure 51 . potential simultaneous sampling serial interface timing vio1 vio2 convert data in 2 clk digital host data in 1 AD7902 adc2 sdi2 sdo2 cnv2 sck2 AD7902 adc1 sdi1 sdo1 cnv1 sck1 11756-324 sdix = 1 t cnvh t conv t cyc cnvx acquisition acquisition t acq t sck t sckl conversion sckx t en t hsdo 1 2 3 14 15 16 t dsdo t dis t sckh sdo1 d15 d14 d13 d1 d0 sdo2 d15 d14 d13 d1 d0 11756-316
data sheet AD7902 rev. b | page 25 of 28 functional saftey co nsiderations the AD7902 contains two physically isolated adcs, making it ideally suited for functional safety applications. because of this isolation, each adc features an inde pendent user interface, an independent reference input, an independent analog input , and independent supplies. physical isolation renders the device suitable for taking verification/ back up measurements while separating the verification adc from the system under control. although the simultaneous sampling section describe s how to operate the device in a simultaneous nature, the circuit is actually composed of two individual signal chains. this separation makes the AD7902 ideal for handling redundant measurement applications. implementing a signal chain with redundant adc mea surement can contribute to a no single error system. figure 52 shows a typical functional safety application circuit consisting of a redundant measurement with the employment of monitoring the inverted signal. the inversion is applied to detect common cause failures where it is expected that the circuit output move s in the same direction during a fault condition , instead of moving in the opposite direction as expected . in addition , the qsop package that houses the device provides acces s to the leads for inspection . figure 52 . typical functional safety block diagram gnd vdd1 vdd2 2.5v ref1 ref2 ref = 2.5v to 5v adc1 in1+ in1? vio1 sdi1 sck1 cnv1 sdo1 sdi1 sck1 cnv1 sdo1 sdi2 vio1 vio2 sck2 cnv2 sdo2 adc2 in2+ in2? vio2 sdi2 sck2 cnv2 sdo2 AD7902 physically isolated adcs 0v to vref ada4841-1 vref ada4841-1 r r r r 1 1756-146
AD7902 data sheet rev. b | page 26 of 28 layout design the printed circuit board (pcb) of the AD7902 such that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the AD7902 , with its analog signals on the left side and its digital signals on the right side, eases this task. avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7902 is used as a shield. do not run fast switching signals, such as cnvx or clocks, near analog signal paths. avoid crossover of digital and analog signals. to avoid signal fidelity issues, take care to ensure monotonicity of digital edges in the pcb layout. use at least one ground plane. it can be shared between or split between the digital and analog sections. in the latter case, join the planes underneath the AD7902 . the AD7902 voltage reference inputs, ref1 and ref2, have a dynamic input impedance. decouple these reference inputs with minimal parasitic inductances by placing the reference decoupling ceramic capacitor in close proximity to (ideally, right up against) the refx and gnd pins and then connecting them with wide, low impedance traces. finally, decouple the power supplies, vddx and viox, with ceramic capacitors, typically 100 nf. place them in close proximity to the AD7902 and connect them using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. see figure 53 for an example of layout following these rules. evaluating performance of the AD7902 other recommended layouts for the AD7902 are outlined in the eval-AD7902sdz user guide . the package for the evaluation board ( eval-AD7902sdz ) includes a fully assembled and tested evaluation board, user guide, and software for controlling the board from a pc via the eval-sdp-cb1z . figure 53. exampl e layout of the AD7902 (top layer) ref1 vdd1 in1+ in1? gnd ref2 vdd2 in2+ in2? gnd vio1 sdi1 sck1 sdo1 cnv1 vio2 sdi2 sck2 sdo2 cnv2 gnd ref ref ref gnd gnd gnd vdd vdd gnd vio vio gnd 11756-147
data sheet AD7902 rev. b | page 27 of 28 outline dimensions figure 54 . 20 - lead shrink small outline package [q sop] (r q - 2 0) dimensions shown in inches and ( millimeters ) ordering guide model 1 temperature range package description package option ordering quantity ad7 902 brq z ? 40 c to +125 c 2 0 - lead shrink small outline package [ q sop ] , tube r q -2 0 5 6 AD7902 brqz - rl7 ? 40c to +125 c 2 0 - lead shrink small outline package [ q sop ] , ree l r q -2 0 1,000 eval - AD7902 sdz evaluation board eval - sdp - cb1z controller board 1 z = rohs compliant part. compliant t o jedec s t andards mo-137-ad controlling dimensions are in inches; millimeter dimensions (in p arentheses) are rounded-off inch equi v alents for reference on l y and are not appropri a te for use in design. 20 1 1 10 1 se a ting plane 0.010 (0.25) 0.004 (0.10) 0.012 (0.30) 0.008 (0.20) 0.025 (0.64) bsc 0.041 (1.04) ref 0.010 (0.25) 0.006 (0.15) 0.050 (1.27) 0.016 (0.41) 0.020 (0.51) 0.010 (0.25) 8 0 coplanarit y 0.004 (0.10) 0.065 (1.65) 0.049 (1.25) 0.069 (1.75) 0.053 (1.35) 0.345 (8.76) 0.341 (8.66) 0.337 (8.55) 0.158 (4.01) 0.154 (3.91) 0.150 (3.81) 0.244 (6.20) 0.236 (5.99) 0.228 (5.79) 09-12-2014- a
AD7902 data sheet rev. b | page 28 of 28 notes ? 2014 C 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11756 - 0- 8/15(b)

▲Up To Search▲

Price & Availability of AD7902

	To Download AD7902 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .